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w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 1 - revision a 01 - 002 t able of contents 1. general descripti on ................................ ................................ ................................ .......... 4 2. features ................................ ................................ ................................ ................................ .. 4 3. pin configuration ................................ ................................ ................................ ................ 5 3.1 ball assignment: lpsdr x 16 ................................ ................................ ................................ ......... 5 3.2 ball assignment: lpsdr x 32 ................................ ................................ ................................ ......... 5 4. pin description ................................ ................................ ................................ ...................... 6 4.1 signal description ................................ ................................ ................................ ............................ 6 4.2 addres sing table ................................ ................................ ................................ ............................. 6 5. block diagram ................................ ................................ ................................ ...................... 7 6. electrical charac teristics ................................ ................................ ........................... 8 6.1 absolute maximum ratings ................................ ................................ ................................ .............. 8 6.2 operating conditions ................................ ................................ ................................ ....................... 8 6.3 capacitance ................................ ................................ ................................ ................................ ..... 8 6.4 dc characteris tics ................................ ................................ ................................ ........................... 9 6.5 automatic temperature compensated self refresh current feature ................................ ............. 11 6.6 ac characteristics and ac operating conditions ................................ ................................ .......... 12 6.6.1 ac characteristics ................................ ................................ ................................ ................................ .... 12 6.6.2 ac test condition ................................ ................................ ................................ ................................ .... 13 6.6.3 ac latency characteristics ................................ ................................ ................................ ...................... 14 7. function descript ion ................................ ................................ ................................ ....... 15 7.1 command function ................................ ................................ ................................ ........................ 15 7.1.1table 1. truth table ................................ ................................ ................................ ................................ .. 15 7.1.2 functional truth table ................................ ................................ ................................ ............................. 16 7.1.3 function truth table for cke ................................ ................................ ................................ .................. 19 7.1.4 bank activate command ................................ ................................ ................................ .......................... 20 7.1.5 bank precharge command ................................ ................................ ................................ ...................... 20 7.1.6 precharge all command ................................ ................................ ................................ .......................... 20 7.1. 7 write command ................................ ................................ ................................ ................................ ....... 20 7.1.8 write with auto precharge command ................................ ................................ ................................ ...... 20 7.1.9 read command ................................ ................................ ................................ ................................ ....... 20 7.1.10 read with auto precharge command ................................ ................................ ................................ ... 20 7.1.11 extended mode register set command ................................ ................................ ............................... 20 7.1.12 mode register set command ................................ ................................ ................................ ................ 21 7.1.13 no - operation command ................................ ................................ ................................ ........................ 21 7.1.14 burst stop command ................................ ................................ ................................ ............................. 21 7.1.15 device deselect command ................................ ................................ ................................ .................... 21 7.1.16 auto refresh command ................................ ................................ ................................ ......................... 21 7.1.17 self refresh entry command ................................ ................................ ................................ ................ 21 7.1.18 self refresh exit command ................................ ................................ ................................ ................... 21 7.1.19 clock suspend mode entry/power down mode entry command ................................ ......................... 21 7.1.20 clock suspend mode exit/power down mode exit command ................................ .............................. 21
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 2 - revision a 01 - 002 7.1.21 data write/output enable, data mask/output disable command ................................ ........................ 22 8.operation ................................ ................................ ................................ ............................... 22 8.1 read operation ................................ ................................ ................................ .............................. 22 8.2 write operation ................................ ................................ ................................ .............................. 22 8.3 precharge ................................ ................................ ................................ ................................ ...... 23 8.3.1 auto prechar ge ................................ ................................ ................................ ................................ ........ 23 8.3.2 read with auto precharge interrupted by a read (with or without auto precharge) ............................. 23 8.3.3 read with auto precharge interrupted by a write (with or without auto precharge) ............................ 24 8.3.4 write with auto precharge interrupted by a read (with or without auto precharge) ............................ 25 8.3.5 write with auto precharge interrupted by a write (with or without auto precharge) .......................... 26 8.4 burst termination ................................ ................................ ................................ ........................... 27 8.5 mode register operation ................................ ................................ ................................ ............... 28 8.5.1 burst length field (a2~a0) ................................ ................................ ................................ ....................... 28 8.5.2 addressing mode select (a3) ................................ ................................ ................................ .................. 28 8.5.3 addressing sequence for sequential mod e ................................ ................................ ............................. 29 8.5.4 addressing sequence for interleave mode ................................ ................................ .............................. 29 8.5.5 addressing sequence example (burst length = 8 and input address is 13) ................................ .......... 30 8.5.6 read cycle latency = 3 ................................ ................................ ................................ ............... 30 8.5.7 latency field (a6~a4) ................................ ................................ ................................ ................... 31 8.5.8 mode register definition ................................ ................................ ................................ .......................... 31 8.6 extended mode register description ................................ ................................ ............................. 32 8.7 simplified state diagram ................................ ................................ ................................ ................ 33 9. control timing wa veforms ................................ ................................ ........................... 34 9.1 command input timing ................................ ................................ ................................ .................. 34 9.2 read timing ................................ ................................ ................................ ................................ ... 35 9.3 control timi ng of input data (x16) ................................ ................................ ................................ . 36 9.4 control timing of output data (x16) ................................ ................................ ............................... 37 9.5 control timing of input data (x32) ................................ ................................ ................................ . 38 9.6 control timing of output data (x32) ................................ ................................ ............................... 39 9.7 mode register set (mrs) cycle ................................ ................................ ................................ ...... 40 9.8 extended mode register set (emrs) cycle ................................ ................................ .................... 41 10. operating timing example ................................ ................................ ............................ 42 10.1 interleaved bank read (burst length = 4, latency = 3) ................................ ...................... 42 10.2 interleaved bank read (burst length = 4, latency = 3, auto precharge) .......................... 43 10.3 interleaved bank read (burst length = 8, latency = 3) ................................ ..................... 44 10.4 interleaved bank read (burst length = 8, latency = 3, auto precharge) .......................... 45 10 .5 interleaved bank write (burst length = 8) ................................ ................................ .................... 46 10.6 interleaved bank write (burst length = 8, auto precharge) ................................ ......................... 47 10.7 page mode read (burst length = 4, latency = 3) ................................ ............................. 48 10.8 page mode read / write (burst length = 8, latency = 3) ................................ .................. 49 10.9 auto precharge read (burst length = 4, latency = 3) ................................ ....................... 50 cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 3 - revision a 01 - 002 10.10 auto precharge write (burst length = 4) ................................ ................................ .................... 51 10.11 auto refresh cycle ................................ ................................ ................................ .................... 52 10.12 se lf refresh cycle ................................ ................................ ................................ ..................... 53 10.13 power down mode ................................ ................................ ................................ ..................... 54 10.14 burst read and single write (burst length = 4, latency = 3) ................................ .......... 55 10.15 deep power down mode entry ................................ ................................ ................................ .. 56 10.16 deep power down mode exit ................................ ................................ ................................ ..... 57 10.17 auto precharge timing (read cycle) ................................ ................................ ......................... 58 10.18 auto precharge timing (write cycle) ................................ ................................ ......................... 59 10.19 timing c hart of read to write cycle ................................ ................................ .......................... 60 10.20 timing chart for write to read cycle ................................ ................................ ......................... 60 10.21 timing chart for burst stop cycle (burst stop command) ................................ ......................... 61 10.22 timing chart for burst stop cycle (precharge command) ................................ ......................... 61 10.23 cke/dqm input timing (write cycle) ................................ ................................ ........................ 62 10.24 cke/dqm input timing (read cycle) ................................ ................................ ........................ 63 11. package dimensio n ................................ ................................ ................................ .......... 64 11.1 : lps dr x 16 ................................ ................................ ................................ ............................... 64 11.2 : lpsdr x 32 ................................ ................................ ................................ ............................... 65 12. ordering information ................................ ................................ ................................ ... 66 13.revision history ................................ ................................ ................................ ................ 67 cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 4 - revision a 01 - 002 1. general descripti on the winbond 256 mb low power sdram is a low power synchronous memory containing 268,435,456 memory cells fabric ated with winbond high performance process technology. it is designed to consum e less power than the ordinary sdram with low power features essential for applications which use batteries. it is available in two organizations: 2 , 097 , 152 words 4 banks 32 bits or 4,194,304 words 4 banks 16 bits. the device operates in a fully synchronous mode, and the output data are synchronized to positive edges of the system clock and is capable of delivering data at clock rate up to 166 m hz . the devic e supports special low power functions such as partial array self refresh (pasr) and automatic temperature compensated self refresh (atcsr). the low power sdram is suitable for 2.5g / 3g cellular phone, pda, digital still camera, mobile game consoles and other handheld applications where large memory density and low power consumption are required. the device operates from 1.8v power supply, and supports the 1.8v lvcmos bus interface. 2. features power supply v dd = 1. 7 v~1.9 5 v v dd q = 1. 7 v~1.9 5 v frequency : 166mhz( - 6) ,133mhz( - 75) programmable partial array self refresh power down mode deep power down mode (dpd) programmable output buffer driver strength automatic temperature compensated self refresh latency: 2 an d 3 burst length: 1, 2, 4 , 8 , and full page refresh: 8k refresh cycle / 64ms interface: lvcmos support package : 54 balls vfbga (x16) 90 balls vfbga (x32) operating temperature range extended ( - 25 c ~ +85 c) industrial ( - 40 c ~ + 85 c) cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 5 - revision a 01 - 002 3. pin configuration 3.1 b all a ssignment : lpsdr x 16 54ball fbga 1 2 3 4 5 6 7 8 9 a vss dq15 vssq vddq dq0 vdd b dq14 dq13 vddq vssq dq2 dq1 c dq12 dq11 vssq vddq dq4 dq3 d dq10 dq9 vddq vssq dq6 dq5 e dq8 nc vss vdd ldqm dq7 f udqm clk cke g a12 a11 a9 ba0 ba1 h a8 a7 a6 a0 a1 a10 j vss a5 a4 a3 a2 vdd (top view) 3.2 ball assignment: lpsdr x 32 90ball fbga 1 2 3 4 5 6 7 8 9 a dq26 dq24 vss vdd dq23 dq21 b dq28 vddq vssq vddq vssq dq19 c vssq dq27 dq25 dq22 dq20 vddq d vssq dq29 dq30 dq17 dq18 vddq e vddq dq31 nc nc dq16 vssq f vss dqm3 a3 a2 dqm2 vdd g a4 a5 a6 a10 a0 a1 h a7 a8 nc nc ba1 a11 j clk cke a9 ba0 k dqm1 nc nc dqm0 l vddq dq8 vss vdd dq7 vssq m vssq dq10 dq9 dq6 dq5 vddq n vssq dq12 dq14 dq1 dq3 vddq p dq11 vddq vssq vddq vssq dq4 r dq13 dq15 vss vdd dq0 dq2 (top view) ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 6 - revision a 01 - 002 4 . pin description 4.1 signal description ball name function description a [ n : 0 ] address multiplexed pins for row and column address. a10 is auto precharge select ba0, ba1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. dq0~dq15 (16) dq0~dq31 (32) data input/ output multip lexed pins for data output and input. chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. row address strobe command input. when sampled at the rising edge of the clock, , and define the operation to be executed. column address strobe referred to write enable referred to udqm / ldqm(x16) dqm0 ~ dqm3 (x32) i/o mask the output buffer is placed at hi - z (with latency of 2 in cl=2, 3;) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency clk clock inputs system clock used to sample inputs on the rising edge of clock. cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode or self refresh mode is entered. vdd power power supply for input buffers and logic circuit inside dram. vss ground ground for input buffers and logic circuit inside dram. vddq power for i/o buffer power supply separated from vdd, used for output buffers to improve noise. vssq ground for i/o buffer separated ground from vss, used for output buffers to improve noise. nc no connection no connection 4. 2 addressing table item 2 5 6 mb number of banks 4 bank address pins ba0,ba1 auto precha r ge pin a10 /ap x 16 row addresses a0 - a12 column addresses a0 - a 8 refresh count 8k x32 row addresses a0 - a1 1 column addresses a0 - a 8 refresh count 8k ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 7 - revision a 01 - 002 5. b lock diagram c l k c k e c s r a s c a s w e a 1 0 a 0 a n b a 0 b a 1 c l o c k b u f f e r c o m m a n d d e c o d e r a d d r e s s b u f f e r r e f r e s h c o u n t e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r m o d e r e g i s t e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 2 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 0 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 3 d a t a c o n t r o l c i r c u i t d q b u f f e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 1 d m n r o w d e c o r d e r r o w d e c o r d e r r o w d e c o r d e r r o w d e c o r d e r d q 0 C d q n d q m
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 8 - revision a 01 - 002 6 . electrical charact eristics 6 .1 a bsolute maximum ratings parameter symbol values units min max voltage on vdd relative to vss vdd 0.3 2.7 v voltage on vddq relative to vss vddq 0.3 2.7 v voltage on any pin relative to vss vin, vout 0.3 2.7 v operating t emperature t c - 2 5 - 40 85 85 c storage temperature tstg 55 150 c short circuit output current iout 50 ma power dissipation pd 1.0 w 6 .2 o perating conditions ( n ote s : 1) parameter symbol min. typ. max. unit supply voltage vdd 1.7 1.8 1.9 5 v supply voltage (for i/o buffer) vddq 1. 7 1.8 1.9 5 v input high level voltage vih 0.8*vddq - vddq + 0.3 v input low level voltage vil - 0.3 - + 0.3 v lv coms output h level voltage (iout = - 0.1 ma ) voh 0.9x v ddq - - v lv cmos output l level voltage (iout = +0.1 ma ) vol - - 0.2 v input leakage current (0v vin vdd, all other pins not under test = 0v) ii(l) - 1 - 1 a output leakage current (output disable , 0v vout vddq) io(l) - 5 - 5 a note: v ih (max) = v dd / v dd q +1.2v for pulse width < 5 n s , v il (min) = v ss / v ss q - 1.2v for pulse width < 5 n s 6 .3 c ap a citance (v dd = 1.7v~1.9 5 v, f = 1 mhz, t a = 25 c) parameter symbol min. max. unit input capacitance (a [ n : 0 ] , b a 0, b a 1, , , , , dqm, cke) ci 1.5 3 .0 pf input capacitance (clk) cclk 1.5 3.5 pf input/output capacitance cio 3.0 5.0 pf note: these parameters are periodically sampled and not 100% tested. ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 9 - revision a 01 - 002 6 .4 dc c haracteristics ( x16) parameter / condition sym. - 6 - 7 5 unit notes max. max. operating current: active mode , 1 bank, bl = 1 , trc = trc ( min ) , i out =0ma , active precharge command cycling without burst operation. idd1 38 35 ma 2, 3, 4 standby current: power - down mode , all banks idle , cke = low . idd2p low power 0.3 0.3 ma 5 normal power 0.4 0.4 standby current: nonpower - down mode , all banks idle , cke = high . idd2n 10 10 ma standby current: active mode; cke = low , cs# = high , all banks active , no accesses in progress . idd3p 3 3 ma 3, 4, 6 standby current: active mode , cke = high , cs# = high , all banks active after trcd met , no accesses in progress . idd3n 20 15 ma 3, 4, 6 operating current: burst mode , all banks active , i out =0ma , read / write command cycling, idd4 75 70 ma 2, 3, 4 auto refresh current: trfc=trfc (min), auto refresh command cycling idd5 50 50 ma 2, 3, 4, 6 deep power down mode izz 10 10 a
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 10 - revision a 01 - 002 (x 32 ) parameter / condition sym. - 6 - 7 5 unit notes max. max. operating current: active mode , 1 bank, bl = 1 , trc = trc ( min ) , i out =0ma , active precharge command cycling without burst operation. idd1 38 35 ma 2, 3, 4 standby current: power - down mode , all banks idle , cke = low . idd2p low power 0.3 0.3 ma 5 normal power 0.4 0.4 standby current: nonpower - down mode , all banks idle , cke = high . idd2n 10 10 ma standby current: active mode; cke = low , cs# = high , all banks active , no accesses in progress . idd3p 3 3 ma 3, 4, 6 standby current: active mode , cke = high , cs# = high , all banks active after trcd met , no accesses in progress . idd3n 20 15 ma 3, 4, 6 operating current: burst mode , all banks active , i out =0ma , read / write command cycling, idd4 75 70 ma 2, 3, 4 operating current: active mode , 1 bank, bl = 1 , trc = trc ( min ) , i out =0ma , active precharge command cycling without burst operation. idd5 50 50 ma 2, 3, 4, 6 standby current: power - down mode , all banks idle , cke = low . izz 10 10 a
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 11 - revision a 01 - 002 6 .5 a utomatic temperature compensated self refresh current feature i dd 6 low power normal power units tcsr range 45 85 45 85 ua full array 200 300 250 400 1/2 array 170 250 200 300 1/4 array 150 220 180 250 note: 1. a full initialization sequence is required before proper device operation is ensured. 2. measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time. 3. enables on - die refresh and address counters. 4. values for idd 6 85c full array and partial array are guaranteed for the entire temperature range. 5. idd6 is typical value.
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 12 - revision a 01 - 002 6 .6 ac c haracteristic s and ac operating conditions 6.6.1 ac c haracteristics *cl= latency ; (note s: 5,6,7) parameter sym - 6 - 75 unit note min. max. min. max. ref/active to ref/active command period trc 60 72.5 - ns 8 active to precharge command period tras 42 100000 50 100000 ns 8 active to read/write command delay time trcd 18 18 - ns 8 read/write(a) to read/write(b)command period tccd 1 1 - clk 8 precharge to active command period trp 18 18 - ns 8 active(a) to active(b) command period trrd 12 15 - ns 8 write recovery time twr 15 15 - ns write - recovery time (last data to read) tldr 1 1 clk clk cycle time cl * = 3 tck 6 1000 7.5 1000 ns cl * = 2 12 1000 12 1000 ns clk high level width tch 2 2.5 - ns clk low level width tcl 2 2.5 - ns access time from clk cl * = 3 tac 5.4 - 5.4 ns cl * = 2 6 - 8 ns output data hold time toh 2 .5 2.5 - ns output data high impedance time cl * = 3 thz 5.4 - 5.4 ns 7 cl * = 2 6 - 6 ns 7 output data low impedance time tlz 1 1 - ns power down mode entry time tsb 0 6 0 7.5 ns transition time of clk (rise and fall) tt 0.3 1 .2 0.3 1.2 ns data - in set - up time tds 1.5 1.5 - ns data - in hold time tdh 1 1 - ns address set - up time tas 1.5 1.5 - ns address hold time tah 1 1 - ns cke set - up time tcks 1.5 1.5 - ns cke hold time tckh 1 1 - ns cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 13 - revision a 01 - 002 parameter sym - 6 - 75 unit note min. max. min. max. command set - up time tcms 1.5 1.5 - ns command hold time tcmh 1 1 - ns refresh time tref 64 64 ms mode register set cycle time trsc 12 15 - ns 8 ref to ref/active command period trfc 72 72 - ns self refresh exit to next valid command delay txsr 115 1 15 - ns 6.6.2 ac test condition symbol p arameter v alue unit v ih(min) input high voltage level (ac) 0.8 x vddq v vil(max) input low voltage level (ac) 0.2 x vddq v vref input signal reference level 0. 5 x vddq v votr outp ut signal reference level 0. 5 x vddq v slew input signal slew rate 1 v/ns transition times are measured between v ih and v il . o u t p u t a c t e s t l o a d z = 5 0 v t t = 0 . 9 v r t = 5 0 v d d q v s s v i h ( m i n ) v r e f v i l ( m a x ) t t t t v o t r c l o a d = 3 0 p f s l e w = ( v i h ( m i n ) - v i l ( m a x ) / t t
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 14 - revision a 01 - 002 note : 1. conditions outside the limits listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect deice reliability . 2. all voltages are referenced to vss and vssq . 3. these parameters depend on the cycle rate. these values are measured at a cycle rate with the minimum values of tck and trc . input signals transition once per tck period. 4. these parameters depend on the output loading. specified values are obtained with the output open. 5. power - up sequence is described in note 9. 6. ac test conditions : (refer to 6.6.2) 7. thz defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 8. these parameters account for the n umber of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number) 9. power up sequence : the sdram should be powered up by the follo wing sequence of operations. a. power must be ap plied to vdd before or at the s a me time as vddq while all input signals are held in the nop state. the clk signal will be applied at power up with power. b. after power - up a pause of at least 200 ua is required. it is required that dqm and cke signals must be held high (vdd levels ) to ensure that the dq output is in high - impedance state. c. all banks must be precharged. d. the mode register set command must be issued to initialize the mode register. e. the e xtended mode register set command m ust be issued to initialize the extended mode register. f. issue two or more auto refresh dummy cycles to stabilize the internal circuitry of the device. the mode register set command can be invoked either before or after the auto refresh dummy cycles. 6.6. 3 ac latency characteristics cke to clock disable (cke latency) 1 cycle dqm to output in high - z (read dqm latency) 2 dqm to input data delay (write dqm latency) 0 write command to input data (write data latency) 0 to command input ( latency) 0 precharge to dq hi - z lead time cl = 2 2 cl = 3 3 precharge to last valid data out cl = 2 1 cl = 3 2 burst stop command to dq hi - z lead time cl = 2 2 cl = 3 3 burst stop command to last valid data out cl = 2 1 cl = 3 2 read with auto precharge command to active/ref command cl = 2 bl+ trp cycle + ns cl = 3 bl+ trp write with auto precharge command to active/ref command cl = 2 bl+1 + trp cl = 3 bl+1 + trp cs
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 15 - revision a 01 - 002 7 . function description 7 . 1 command function 7.1.1 table 1. truth table (note (1) and (2) ) s y mbol command device st ate c ke n - 1 cken dqm(5) bs0, bs1 a10 address act bank activate idle (3) h x x v v v l l h h pre bank precharge any h x x v l x l l h l prea precharge all any h x x x h x l l h l writ write active (3) h x x v l v l h l l writa write with auto precharge active (3) h x x v h v l h l l read read active (3) h x x v l v l h l h reada read with auto precharge active (3) h x x v h v l h l h mrs mode register set idle h x x v v v l l l l emrs extended mode register set idle h x x v v v l l l l nop no - operation any h x x x x x l h h h bst burst stop active (4) h x x x x x l h h l dsl device deselect any h x x x x x h x x x aref auto - refresh idle h h x x x x l l l h self self - refresh entry idle h l x x x x l l l h selex self - refresh exit idle (self refresh) l h x x x x h x x x l h h h cse clock suspend mode entry active h l x x x x x x x x pd power down mode entry idle/active (6) h l x x x x h x x x l h h h csex clock suspend mode exit active l h x x x x x x x x pdex power down mode exit any (power down) l h x x x x h x x x l h h x de data write/output enable active h x l x x x x x x x dd data write/output disable active h x h x x x x x x x dpd deep power down mode entry idle h l x x x x l h h l dpde deep power down mode exit idle (dpd) l h x x x x x x x x note 1. v = valid, = dont care, l = low level, h = high level 2. cken signal is input level when commands are issued. cken - 1 signal is input level one clock cycle before the commands are issued. 3. these are state designated by the bs0, bs1 signals. 4. device state is full page burst operation. 5. x32: dqm0 - 3, x16 : ldqm / udqm 6. power down mode can not entry in the burst cycle. when this command assert in the burst cycle, device state is clock suspend mode. ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 16 - revision a 01 - 002 7.1.2 functional truth table (see note 1 at the end of this table) current state address command action notes idle h x x x x ds l nop l h h x x nop/bs t nop l h l h bs , ca , a1 0 read/read a illeg al 3 l h l l bs, ca, a1 0 w rit/writ a illeg al 3 l l h h bs, r a ac t r o w activating l l h l bs , a1 0 pre/pre a nop l l l h x aref/sel f refresh or sel f r efres h 2 l l l l op - cod e mrs/emr s mod e registe r a c cessin g 2 ro w active h x x x x ds l nop l h h x x nop/bs t nop l h l h bs, ca, a1 0 read/read a begin read: det e rmine a p 4 l h l l bs, ca, a1 0 w rit/writ a begin write: det e rmine a p 4 l l h h bs , r a ac t illega l 3 l l h l bs , a1 0 pre/pre a precharg e 5 l l l h x aref/sel f illeg a l l l l l op - cod e mrs/emr s illegal read h x x x x ds l continue burst t o end l h h h x no p continue burst t o end l h h l x bs t burs t stop l h l h bs, ca, a1 0 read/read a term b u rst, n ew read: det e rmin e a p 6 l h l l bs, ca, a1 0 w rit/writ a term b u rst, beg i n write: det e rmi n e a p 6,7 l l h h bs , r a ac t illega l 3 l l h l bs, a1 0 pre/pre a term b u rst, pre c harging l l l h x aref/sel f illeg a l l l l l op - cod e mrs/emr s illeg a l write h x x x x ds l continue burst t o end. l h h h x no p continue burst t o end l h h l x bs t burst stop, r o w ac tive l h l h bs, ca, a1 0 read/read a term b u rst, star t read: det e rmin e a p 6, 7 l h l l bs, ca, a1 0 w rit/writ a term b u rst, n ew write: det e rmin e a p 6 l l h h bs , r a ac t illega l 3 l l h l bs, a1 0 pre/pre a term b u rst. pre c hargin g 8 l l l h x aref/sel f illega l l l l l op - cod e mrs/emr s illega l ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 17 - revision a 01 - 002 current state address command action notes read w i t h auto precharge h x x x x ds l continue burst t o end l h h h x no p continue burst t o end l h h l x bs t illegal l h l h bs , ca , a1 0 read/read a illegal 3 l h l l bs, ca, a1 0 w rit/writ a illegal 3 l l h h bs , r a ac t illegal 3 l l h l bs , a1 0 pre/pre a illegal 3 l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal write w i th a u to precharge h x x x x ds l continue burst t o end l h h h x no p continue burst t o end l h h l x bs t illegal l h l h bs , ca , a1 0 read/read a illegal 3 l h l l bs, ca, a1 0 w rit/writ a illegal 3 l l h h bs , r a ac t illegal 3 l l h l bs , a1 0 pre/pre a illegal 3 l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal precharging h x x x x ds l no p idle af t e r t rp l h h h x no p no p idle af t e r t rp l h h l x bs t illegal l h l h bs , ca , a1 0 read/read a illegal 3 l h l l bs, ca, a1 0 w rit/writ a illegal 3 l l h h bs , r a ac t illegal 3 l l h l bs , a1 0 pre/pre a no p idle af t e r t rp l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal ro w activating h x x x x ds l no p r o w active after t rcd l h h h x no p no p r o w active after t rcd l h h l x bs t illegal l h l h bs , ca , a1 0 read/read a illegal 3 l h l l bs, ca, a1 0 w rit/writ a illegal 3 l l h h bs , r a ac t illegal 3 l l h l bs , a1 0 pre/pre a illegal 3 l l l h x aref/sel f illegal l l l l op - cod e mrs/emr s illegal ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 18 - revision a 01 - 002 current state address command action notes write recover i ng h x x x x ds l no p maintai n r o w active afte r t w r l h h h x no p no p maintai n r o w active afte r t w r l h h l x bs t no p maintai n r o w active afte r t w r l h l h bs , ca , a1 0 read/read a begin rea d 7 l h l l bs, ca, a1 0 w rit/writ a begin n e w write l l h h bs , r a ac t illega l 3 l l h l bs , a1 0 pre/pre a illega l 3 l l l h x aref/sel f illega l l l l l op - cod e mrs/emr s illega l write recover i ng w i th auto precha r ge h x x x x ds l no p ent e r p rec harge afte r t w r l h h h x no p no p ent e r p rec harge afte r t w r l h h l x bs t no p ent e r p rec harge afte r t w r l h l h bs , ca , a1 0 read/read a illega l 3 l h l l bs, ca, a1 0 w rit/writ a illega l 3 l l h h bs , r a ac t illega l 3 l l h l bs , a1 0 pre/pre a illega l 3 l l l h x aref/sel f illega l l l l l op - cod e mrs/emr s illega l refreshing h x x x x ds l no p idle af t e r t rfc l h h h x no p no p idle af t e r t rfc l h h l x bs t no p idle af t e r t rfc l h l x x read/wri t illegal l l h x x act/pre/pre a illegal l l l x x aref/self/mrs/ emrs illegal mode register accessing h x x x x ds l no p idle af t e r t rsc l h h h x no p no p idle af t e r t rsc l h h l x bs t illega l l h l x x read/wri t illega l l l x x x act/pre/prea/ aref/self/mrs/ emrs illega l note: 1. all entries assume that cke was active (high level) during the preceding clock cycle and the current clock cycle (cken - 1 = cken = 1) 2. illegal if any bank is not idle. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (bs), depending on the state of that bank. 4. illegal if trcd is not satisfied. 5. illegal if tras is not satisfied. 6. must satisfy burst interrupt condition. 7. must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. must mask preceding data which dont satisfy twr. remark: h = high level, l = low level, x = high or low level (dont care), v = valid data ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 19 - revision a 01 - 002 7.1.3 function truth table for cke current state cke address action notes n - 1 n self refresh h x x x x x x n/a l h h x x x x exit self refresh idle after trfc l h l h h h x exit self refresh idle after trfc l h l h l x x illegal l h l l x x x illegal l l x x x x x maintain self refresh power - down h x x x x x x n/a l h h x x x x exit power down idle after 1 clock cycle l h h h x l l x x x x x maintain power - down deep power - down h x x x x x x n/a l h x x x x x exit deep power - down exit sequence l l x x x x x maintain deep power - down all banks idle h h x x x x x refer to function truth table h l h x x x x enter power - down 2 h l l h h h x enter power - down 2 h l l h h l x enter deep power - down 3 h l l l l h x self refresh 1 h l l h l x x illegal h l l l x x x illegal l x x x x x x power - down 2 row active h h x x x x x refer to function truth table h l h x x x x enter power down 2 h l l h h h x enter power down 2 h l l l l h x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x power - down row active or maintain pd any state other than listed above h h x x x x x refer to function truth table note: 1. self refresh can enter only from the all banks idle state. 2. power - down can enter only from the all banks idle or row active state. 3. deep power - down can enter only from the all banks idle state. remark: h = high level, l = low level, x = high or low level (dont care), v = valid data ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 20 - revision a 01 - 002 7 . 1.4 bank activate c ommand ( = l, = h, = h, b a 0, b a 1 = bank, a0~a n = row address) the bank activate command activates the bank designated by the bs (bank select) signal. row addresses are latched on a0~a n when this command is issued and the cell data is read out to the sense amplifiers. the maximum time that each bank can be held in the active state is specified as tras (max). 7 . 1.5 bank precharge c ommand ( = l, = h, = l, b a 0, b a 1 = bank, a10 =l ) the bank precharge command is used to close (or precharge) the bank that is activated. using this command, systems can designated the bank to be closed by specifying the bs address bit setting in the command set. a precharge command can be used to precharg e each bank separately (bank precharge) or all four banks simultaneously (precharge all). after the bank precharge command is issued, any one bank can close, and the closed bank transitions from the active state to the idle state. to re - activate the closed bank, a system has to wait the minimum trp delay after issuing the precharge command before issuing the active command for the device to complete the precharge operation. 7 . 1.6 precharge all c ommand ( = l, = h, = l, b a 0, b a 1 = dont care, a10 =h) the precharge all command is used to precharge all banks simultaneously. after this command is issued, all four banks close a nd transition from the active state to the idle state. 7 . 1.7 write c ommand ( = h, = l, = l, b a 0, b a 1 = bank, a10 = l) the write command initiates a write operation to the bank selected by b a 0 and b a 1 address inputs. the write data is latched at the positive edge of clk. users should preprogram the length of the write data (burst length) and the column access sequence (addressing mode) by setting the mode resister at power - up prior to using the write command. 7 . 1.8 write with auto precharge c ommand ( = h, = l, = l, b a 0, b a 1 = bank, a10 = h) the write with auto precharge command performs the precharge operation automatically after the write operation. the internal precharge starts in the cycles immediately following the cycle in which the last data is written independent of latency. 7 . 1.9 read c ommand ( = h, = l, = h, b a 0, b a 1 = bank, a10 = l) the read command performs a read operation to the bank designated by b a 0 - 1 . the read data is issued sequentially synchronized to the positive edges of clk. the length of read data (burst length), addressing mode and latency (access time from command in a clock cycle) must be programm ed in the mode register at power - up prior to the write operation. 7 . 1.10 read with auto precharge c ommand ( = h, = l, = h, b a 0, b a 1 = bank, a10 =h) the read with auto precharge command automatically performs the precharge operation after the read operation. when the latency = 3, the internal precharge starts two cycles before the last data is output. when the latency = 2, the internal precharge starts one cycle before the last data is output. 7 . 1.11 extended mode register set c ommand ( = l, = l, = l, b a 0, b a 1, a0~a n = register data) the extended mode register set command is designed to support partial array self refresh, temperature compensated self refresh, and output driver strength/size by allowing users to program each value by setting predefined address bits. the defa ult values in th e extended mode register after power - up are undefined; therefore this command must be issued during the power - up sequence. also, this command can be issued while all banks are in the idle state. ras we cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 21 - revision a 01 - 002 7 . 1.12 mode register set c ommand ( = l, = l, = l, b a 0, b a 1, a0~a n = register data) the mode register set command is used to program the values of latency, addressing mode and burst length in the mode register. the defaul t values in the mode register after power - up are undefined; therefore this command must be issued during the power - up sequence and re - issued after the deep power down exit command. also, this command can be issued while all banks are in the idle state. 7 . 1.13 no - operation c ommand ( = h, = h, = h) the no - operation command is used in cases such as preventing the device from registering unintended commands. the device performs no operation when this command is registered. this command is functionally equivalent to the device deselect command . 7 . 1.14 burst stop c ommand ( = h, = h, = l) the burst stop command is used to stop the already activated burst operation. the activated page is left unclosed and future commands can be issued to access the same page of the active bank. if this command is issued during a burst read operation, the read data will go to a hi - z state after a delay equal to the latency. if a burst stop command is issued during a burst write operat ion, then the burst data is terminated and data bus goes to hi - z at the same clock that the burst command is activated. any remaining data from the burst write cycle is ignored. 7 . 1.15 device deselect c ommand ( = h) the device deselect command disables the command decoder so that the , , and address inputs are ignored. this command is similar to the no - operation command. 7 . 1.16 auto refresh c ommand ( = l, = l, = h, cke = h, b a 0, b a 1, a0~a n = dont care) the auto refresh command is used to refresh the row address provided by the internal refresh counter. the refresh operation m ust be performed 8192 times within 64 ms. the next command can be issued after trc from the end of the auto refresh command. when t he auto refresh command is issued, all banks must be in the idle state. the auto refresh operation is equivalent to the - before - operation in a conventional dram. 7 . 1.17 self refresh entry c ommand ( = l, = l, = h, cke = l, b a 0, b a 1, a0~a n = dont care) when the self refresh entry command is issued, the device enters the self refresh mode. while the device is in self refresh m ode, the device automatically refreshes memory cells, and all input and i/o buffers (except the cke buffer) are disabled. by asser t ing the cke signal high (and by issuing the self refresh exit command), the device exits the self refresh mode. 7 . 1.18 self refresh exit c ommand (cke = h, = h or cke = h, = h, = h) this command is issued to exit out of the self refresh mode. one trc delay is required prior to issuing any subsequent comman d from the end of the self refresh exit command. 7 . 1.19 clock suspend mo de entry/power down mode entry c ommand (cke = l) the int ernal clk is suspended for one cycle when this command is issued (when cke is asserted low). the device state is held intact while the clk is suspended. on the other hand, when the device is not operating the burst cycle, this command performs entry into power down mode. all input and output buffers (except the cke buffer) are turned off in power down mode. 7 . 1.20 clock suspend mode exit/power down mode exit c ommand (cke = h) when the internal clk has been suspended, operation of the internal clk is re sumed by providing this command (asserting cke high). when the device is in power down mode, the device exits this mode and all disabled buffers are turned on to the acti ve state. any subsequent commands can be issued after one clock cycle from the end o f this command. ras we cs cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 22 - revision a 01 - 002 7 . 1.21 data write/output en able, data mask/output disable c ommand (dqm = l/h or ldqm, udqm = l/h or dqm0 - 3=l/h) during a write cycle, the dqm or ldqm, udqm or dqm0 - 3 signals mask write data. each of these signals control the input buffers per byte. during a read cycle, the dqm or ldqm, udqm or dqm0 - 3 signals control of the output buffers per byte. i/o org. m ask p in m asked dqs 16 ldqm dq0~dq7 udqm: dq8~dq15 32 dqm0: dq0~dq7 dqm1: dq8~dq15 dqm2: dq16~dq23 dqm3: dq24~dq31 8. operation 8.1 read operation issuing the bank activate command to the idle bank puts it into the active state. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially, synchronized to the positive edges of clk (a burst read operation). the initial read data becomes available after latency from the issuing of the read command. the latency must be set in the mode register at power - up. in addition, the burst length of read data and addressing mode must be set. each bank is held in the active state unless the pre charge command is issued, so that the sense amplifiers can be used as secondary cache. when the read with auto precharge command is issued, the precharge operation is performed automatically after the read cycle, then the bank is switched to the idle stat e. this command cannot be interrupted by any other commands. also, when the burst length is 1 and t rcd (min), the timing from the command to the start of the auto precharge operation is shorter than t ras (min). in this case, t ras (mi n) must be satisfied by extending t rcd . when the precharge operation is performed on a bank during a burst read operation, the burst operation is terminated. when the burst length is full - page, column data is repeatedly read out until the burst stop comm and or precharge command is issued. 8.2 write operation issuing the write command after t rcd from the bank activate command, the input data is latched sequentially, synchronizing with the positive edges of clk after the write command (burst write operat ion). the burst length of the write data (burst length) and addressing mode must be set in the mode register at power - up. when the write with auto precharge command is issued, the precharge operation is performed automatically after the write cycl e, then the bank is switched to the idle state. this command cannot be interrupted by any other command for the entire burst data dur ation. also, when the burst length is 1 and t rcd (min), the timing from the command to the start of the auto precharge operation is shorter than tras (min). in this case, t ras (min) must be satisfied by extending t rcd . when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated. when the burst length is full - page, the input data is repeatedly latched until the burst stop command or the precharge command is issued. when the burst read and single write mode is selected, the write burst length is 1 regardless of the read burst length. ras cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 23 - revision a 01 - 002 8.3 precharge there are two commands which perform the precharge operation: bank precharge and precharge all. when the bank precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. the bank precharge command can prechar ge one bank independently of the other bank and hold the unprecharged bank in the active state. the maximum time each bank can be held in the active state is specified as t ras (max). therefore, each bank must be precharged within t ras (max) from the bank a ctivate command. the precharge all command can be used to precharge all banks simultaneously. even if banks are not in the active state, the p recharge all command can still be issued. in this case, the precharge operation is performed only for the active bank and the precharged bank is then switched to the idle state. 8.3.1 auto precharge auto precharge is a feature that performs the same individual - bank precharge function described previously, without requiring an explicit command. this is accomplished b y using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of th e read or write burst . auto precharge en sures that the precharge is initiated at the earliest valid stage within a burst. another command cannot be issued to the same bank until the precharge time (trp) is completed. this is determined as if an explicit precharge command was issued at the earlie st possible time. winbond sdram supports concurrent auto precharge; cases of concurrent auto precharge for reads and writes are defined below. 8.3.2 read with auto precharge interrupted by a read (with or without auto precharge) a read to bank m will inte rrupt a read on bank n following the programmed cas latency. the precharge to bank n begins when the read to bank m is registered. c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s d q i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p i d l e d o u t a b a n k n , c o l a b a n k m , c o l d t r p - b a n k m p r e c h a r g e t r p - b a n k n r e a d - a p b a n k m r e a d w i t h b u r s t o f 4 i n t e r r u p t b u r s t , p r e c h a r g e r e a d w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e r e a d - a p b a n k n c l = 3 ( b a n k n ) c l = 3 ( b a n k m ) d o n t c a r e n o t e : 1 . d q m i s l o w . d o u t a + 1 d o u t d d o u t d + 1
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 24 - revision a 01 - 002 8.3.3 read with auto precharge interrupted by a write (with or without auto precharge) a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n begins when the write to bank m is registered. c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p i d l e b a n k n , c o l a b a n k m , c o l d t w r - b a n k m w r i t e - b a c k t r p - b a n k n w r i t e - a p b a n k m w r i t e w i t h b u r s t o f 4 i n t e r r u p t b u r s t , p r e c h a r g e r e a d w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e r e a d - a p b a n k n d o u t a d o n t c a r e d q m d q 1 c l = 3 ( b a n k n ) n o t e : 1 . d q m i s h i g h a t t 2 t o p r e v e n t d o u t a + 1 f r o m c o n t e n d i n g w i t h d i n d a t t 4 . d i n d d i n d + 1 d i n d + 2 d i n d + 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 25 - revision a 01 - 002 8.3.4 write with auto precharge interrupted by a read (with or without auto precharge) a read to bank m will interrupt a write on bank n when registered, with the data - out appearing cl later. the precharge to bank n will begin after twr is met, where twr b egins when the read to bank m is registered. the last valid write to bank n will be data in registered one clock prior to the read to bank m. c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s d q i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p p r e c h a r g e d o u t d b a n k n , c o l a b a n k m , c o l d t r p - b a n k m t r p - b a n k n r e a d - a p b a n k m r e a d w i t h b u r s t o f 4 i n t e r r u p t b u r s t , w r i t e - b a c k w r i t e w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e w r i t e - a p b a n k n c l = 3 ( b a n k m ) d o n t c a r e n o t e : 1 . d q m i s l o w . t w r - b a n k n d i n a d i n a + 1 d o u t d + 1
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 26 - revision a 01 - 002 8.3.5 write with auto precharge interrupted by a write (with or without auto pre charge) a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after twr is met, where twr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m. c l k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c o m m a n d b a n k n b a n k m a d d r e s s d q i n t e r n a l s t a t e s n o p n o p n o p n o p n o p n o p p r e c h a r g e b a n k n , c o l a b a n k m , c o l d t w r - b a n k m t r p - b a n k n w r i t e - a p b a n k m w r i t e w i t h b u r s t o f 4 i n t e r r u p t b u r s t , w r i t e - b a c k w r i t e w i t h b u r s t o f 4 p a g e a c t i v e p a g e a c t i v e w r i t e - a p b a n k n d o n t c a r e n o t e : 1 . d q m i s l o w . t w r - b a n k n w r i t e - b a c k d i n a d i n a + 1 d i n a + 2 d i n d d i n d + 1 d i n d + 2 d i n d + 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 27 - revision a 01 - 002 8.4 burst termination the read or write command can be issued on any clock cycle. whenever a read operation is to be interrupted by a write command , the output data must be masked by dqm to avoid i/o conflict. also, when a write operation is to be interrupted by a read command, only the input data before the read command is enable and the input data after the read command is disabled. - read interrupted by a precharge a precharge com mand can be issued to terminate a burst cycle early. when a burst read cycle is interrupted by a precharge command, the read operation is terminated after ( latency - 1) clock cycles from the precharge command. - write interrupted by a precharge a burst write cycle can be interrupted by a precharge command, the input circuit is reset at the same clock cycle at which th e precharge command is issued. in this case, the dqm signal must be asserted high to prevent writing the invalid data t o the cell array. - read interrupted by a burst stop when the burst stop command is issued for the bank in a burst cycle, the burst operation is terminated. when the burst stop command is issued during a burst read cycle, the read operation is terminated after clock cycle of ( latency - 1) from the burst stop command. - write interrupted by a burst stop when the burst stop command is issued during a burst write cycle, the write operation is terminated at the same clock cycle t hat the burst stop command is issued. - write interrupted by a read a burst of write operation can be interrupted by a read command. the read command interrupts the write operation on the same clock that the read command is issued. all the burst writes that are presented on the data bus before the read command is issued will be written to the memory. any remaining burst writes will be ignored once the read command is activated. there must be a t least one clock bubble (hi - z state) on the data bus to avoid bus con tention. - read interrupted by a write a burst of read operation can be interrupted by a write command by driving output drivers in a hi - z state using dqm before write to avoid data conflict. dqm should be utilized if there is data from a red command on the first and second cycles of the subsequent write cycles to ensure the read data are tri - stated. from the third clock cycle, the write command will control the data bus and dqm is not needed. cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 28 - revision a 01 - 002 8.5 mode register operation the mode register designates the operation mode for the read or write cycle. this register is divided into three fields; a bu rst length field to set the length of burst data, an addressing mode selected bits to designate the column access sequence in a bur st cycle, and a latency field to set the access time in clock cycle. the mode register is programmed by the mode register set command when all banks are in the idle state. the data to be set in the mode register is transferred using the a0~a n , b a 0, b a 1 address inputs. the initial value of the mode register after power - up is undefined; therefore the mode register set command must be issued before proper operation. 8.5 .1 burst length field (a2~a0) this field specifies the data lengt h for column access using the a2~a0 pins and sets the burst length to be 1, 2, 4, 8, words, or full - page. a2 a1 a0 b ust l ength 0 0 0 1 word 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 1 1 full - page 8.5 .2 addressing mode select (a3) the addressing mode can be one of two modes; interleave mode or sequential mode. when the a3 bit is 0, sequential mode is selected. when the a3 bit is 1, interleave mode is selected. both addressing modes support burst length of 1, 2, 4 and 8 word s. additi onally, sequential mode supports the full - page burst. a3 a ddressing m ode 0 sequential 1 interleave cas
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 29 - revision a 01 - 002 ? addressing sequence of sequential mode a column access is performed by incrementing the column address input to the device. the address is varied by the burst lengt h shown as below table. 8.5 .3 addressing se quence for sequential m ode ? addressing sequence of interleave mode a column access is started from the input column address and is performed by inverting the address bits in the sequence shown as below t able. 8.5 .4 addressing s equence for interleave m ode d a t a a c c e s s a d d r e s s b u r s t l e n g t h d a t a 0 d a t a 1 d a t a 2 d a t a 3 d a t a 4 d a t a 5 d a t a 6 d a t a 7 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 8 w o r d s ( a d d r e s s b i t s i s a 2 , a 1 , a 0 ) n o t c a r r i e d f r o m a 2 t o a 3 4 w o r d s ( a d d r e s s b i t s i s a 1 , a 0 ) n o t c a r r i e d f r o m a 1 t o a 2 2 w o r d s ( a d d r e s s b i t s i s a 0 ) n o t c a r r i e d f r o m a 0 t o a 1 d a t a a c c e s s a d d r e s s b u r s t l e n g t h d a t a 0 d a t a 1 d a t a 2 d a t a 3 d a t a 4 d a t a 5 d a t a 6 d a t a 7 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 8 w o r d s 4 w o r d s 2 w o r d s
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 30 - revision a 01 - 002 8.5 .5 addressing s equence e xample (burst length = 8 and i nput a ddress is 13 ) data i nterleave mode s equential mode a8 a7 a6 a5 a4 a3 a2 a1 a0 add add calculated using a2, a1 and a0 bits not carry from a2 to a3 bit. data0 0 0 0 0 0 1 1 0 1 13 13 13 data1 0 0 0 0 0 1 1 0 0 12 13 + 1 14 data2 0 0 0 0 0 1 1 1 1 15 13 + 2 15 data3 0 0 0 0 0 1 1 1 0 14 13 + 3 8 data4 0 0 0 0 0 1 0 0 1 9 13 + 4 9 data5 0 0 0 0 0 1 0 0 0 8 13 + 5 10 data6 0 0 0 0 0 1 0 1 1 11 13 + 6 11 data7 0 0 0 0 0 1 0 1 0 10 13 + 7 12 8.5 .6 read cycle latency = 3 cas r e a d 1 3 q 0 0 1 2 3 4 5 6 7 8 1 0 9 1 1 q 1 q 2 q 3 q 4 q 5 q 6 q 7 1 3 1 2 1 5 1 4 9 8 1 1 1 0 1 3 1 4 1 5 8 9 1 0 1 1 1 2 d a t a a d d r e s s { i n t e r l e a v e m o d e s e q u e n t i a l m o d e c o m m a n d a d d r e s s d q 0 ~ d q 7
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 31 - revision a 01 - 002 8.5 .7 latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first data read. the minimum va lues of latency depends on the frequency of clk. the minimum value which satisfies the following formula must be set in this field. a6 a5 a4 latency 0 1 0 2 clock 0 1 1 3 clock ? reserved bits ( a7, a8, a10, a11, a n , b a 0, b a 1) these bits are reserved for future operations. they must be set to 0 for normal operation. ? single write mode ( a9 ) this bit is used to select the write mode. when the an bit is 0, burst read and burst write mode are selected. when the an bit is 1, burst read and single write mode are selected. a9 write mode 0 burst read and burst write 1 burst read and single write 8.5 .8 mode register definition cas a 0 a 3 a 0 a d d r e s s i n g m o d e a 0 0 a 0 s e q u e n t i a l a 0 1 a 0 i n t e r l e a v e a 0 a 9 s i n g l e w r i t e m o d e a 0 0 a 0 b u r s t r e a d a n d b u r s t w r i t e a 0 1 a 0 b u r s t r e a d a n d s i n g l e w r i t e a 0 a 0 a 2 a 1 a 0 a 0 0 0 0 a 0 0 0 1 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 1 0 1 a 0 1 1 0 a 0 1 1 1 a 0 b u r s t l e n g t h a 0 s e q u e n t i a l a 0 i n t e r l e a v e 1 a 0 1 a 0 2 a 0 2 a 0 4 a 0 4 a 0 8 a 0 8 a 0 r e s e r v e d a 0 r e s e r v e d a 0 f u l l p a g e a 0 c a s l a t e n c y a 0 r e s e r v e d 2 a 0 3 r e s e r v e d a 0 a 6 a 5 a 4 a 0 0 0 0 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 0 0 1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 b u r s t l e n g t h a d d r e s s i n g m o d e c a s l a t e n c y a 8 r e s e r v e d a 0 a 7 a 0 a 9 a 0 w r i t e m o d e a 1 0 a 0 a 1 1 b a 0 " 0 " " 0 " a 0 r e s e r v e d " 0 " " 0 " b a 1 " 0 " " 0 " " 0 " a 1 2 r e s e r v e d r e s e r v e d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 32 - revision a 01 - 002 8.6 extended mode register description the extended mode register designates the operation condition while sdram is in self refresh mode and selects the output driver strength as full, 1/2, 1/4, or 1/8 strength. the register is divided into t wo fields; (1) partial array self refresh field selects h ow much banks or which part of a bank need to be refreshed during self refresh. (2) driver strength selected bit to control the size of output buffer. the initial value of the extended mode register after power - up is full driver strength, and all banks are refreshed during self refresh mode. e x t e n d e d m o d e r e g i s t e r s e t a 0 a 1 a 2 a 3 a 4 a 5 a 6 p a r t i a l a r r a y s e l f r e f r e s h a 8 a 7 a 9 a 1 0 a 1 1 b a 0 " 0 " " 0 " r e s e r v e d " 1 " b a 1 " 0 " " 0 " o u t p u t d r i v e r " 0 " " 0 " a 2 a 1 a 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 r e s e r v e d s e l f - r e f r e s h c o v e r a g e a l l b a n k s r e s e r v e d r e s e r v e d a 6 a 5 d r i v e r s t r e n g t h f u l l s t r e n g t h 1 / 2 s t r e n g t h 0 0 0 1 1 0 1 1 1 / 4 s t r e n g t h 1 / 8 s t r e n g t h a 1 2 " 0 " r e s e r v e d r e s e r v e d " 0 " " 0 " b a n k 0 ( b a 1 = b a 0 = 0 ) b a n k s 0 a n d 1 ( b a 1 = 0 ) r e s e r v e d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 33 - revision a 01 - 002 8.7 s implified state diagram
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 34 - revision a 01 - 002 9 . control t iming waveforms 9 .1 command input timing t c k c l k a d d r e s s b a 0 , b a 1 v i h v i l t c m h t c m s t c h t c l t t t t t c k s t c k h t c k h t c k s t c k s t c k h c s r a s c a s w e c k e t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 35 - revision a 01 - 002 9 .2 r ead timing r e a d c a s l a t e n c y t a c t l z t a c t o h t h z t o h b u r s t l e n g t h r e a d c o m m a n d c l k c s r a s c a s w e a d d r e s s b a 0 , b a 1 d q o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 36 - revision a 01 - 002 9 .3 control timing of input data (x16) t c m h t c m s t c m h t c m s t d s t d h t d s t d h t d s t d h t d s t d h t c k h t c k s t c k h t c k s t d s t d h t d s t d h t d h t d s t d s t d h c l k l d q m d q 0 ~ d q 7 ( w o r d m a s k ) ( c l o c k m a s k ) c l k c k e d q 0 ~ d q 7 d q 8 ~ d q 1 5 t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d h t d s t d s t d h d q 8 ~ d q 1 5 u d q m t c m h t c m s t c m h t c m s i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 37 - revision a 01 - 002 9 .4 control timing of output data (x16) t c m h t c m s t c m h t c m s t o h t a c t o h t a c t o h t h z t l z t a c t o h t a c t c k h t c k s t c k h t c k s t o h t a c t o h t a c t o h t a c t o h t a c c l k ( o u t p u t e n a b l e ) ( c l o c k m a s k ) l d q m c k e c l k o p e n d q 0 ~ d q 7 d q 0 ~ d q 7 t c m h t c m s t c m h t c m s u d q m d q 8 ~ d q 1 5 o p e n t o h t a c t o h t a c t o h t a c t l z t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 8 ~ d q 1 5 t o h t h z o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 38 - revision a 01 - 002 9 .5 control timing of input data (x32) t c m h t c m s t c m h t c m s t d s t d h t d s t d h t d s t d h t d s t d h t c k h t c k s t c k h t c k s t d s t d h t d s t d h t d h t d s t d s t d h c l k d q m 0 d q 0 ~ d q 7 ( w o r d m a s k ) ( c l o c k m a s k ) c l k r a s d q 0 ~ d q 7 d q 8 ~ d q 1 5 t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d h t d s t d s t d h d q 8 ~ d q 1 5 d q m 1 t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h * d q m 2 , 3 = l d q 1 6 ~ d q 2 3 d q 2 4 ~ d q 3 1 t c m h t c m s t c m h t c m s * d q m 2 , 3 = l t d s t d h t d s t d h t d h t d s t d s t d h d q 1 6 ~ d q 2 3 t d s t d h t d s t d h t d h t d s t d s t d h d q 2 4 ~ d q 3 1 i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d i n p u t d a t a v a l i d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 39 - revision a 01 - 002 9 .6 control timing of output data (x32) t c m h t c m s t c m h t c m s t o h t a c t o h t a c t o h t h z t l z t a c t o h t a c t c k h t c k s t c k h t c k s t o h t a c t o h t a c t o h t a c t o h t a c c l k ( o u t p u t e n a b l e ) ( c l o c k m a s k ) d q m 0 c k e c l k o p e n d q 0 ~ d q 7 d q 0 ~ d q 7 t c m h t c m s t c m h t c m s d q m 1 d q 8 ~ d q 1 5 o p e n t o h t a c t o h t a c t o h t a c t l z t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 8 ~ d q 1 5 d q m 2 , 3 = l t o h t a c t o h t a c t o h t a c t o h t h z t o h t a c t l z t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 1 6 ~ d q 2 3 d q 2 4 ~ d q 3 1 d q m 2 , 3 = l t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c t o h t a c d q 1 6 ~ d q 2 3 d q 2 4 ~ d q 3 1 o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d o u t p u t d a t a v a l i d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 40 - revision a 01 - 002 9 .7 mode register set (mrs) c y cle a 0 a 1 a 2 a 3 a 4 a 5 a 6 b u r s t l e n g t h a d d r e s s i n g m o d e c a s l a t e n c y a 8 r e s e r v e d a 0 a 7 a 0 a 9 a 0 w r i t e m o d e a 1 0 b a 0 a 0 a 1 1 a 0 b a 1 0 0 a 0 a 3 a 0 a d d r e s s i n g m o d e a 0 0 a 0 s e q u e n t i a l a 0 1 a 0 i n t e r l e a v e a 0 a 9 s i n g l e w r i t e m o d e a 0 0 a 0 b u r s t r e a d a n d b u r s t w r i t e a 0 1 a 0 b u r s t r e a d a n d s i n g l e w r i t e a 0 a 0 a 2 a 1 a 0 a 0 0 0 0 a 0 0 0 1 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 1 0 1 a 0 1 1 0 a 0 1 1 1 a 0 b u r s t l e n g t h a 0 s e q u e n t i a l a 0 i n t e r l e a v e 1 a 0 1 a 0 2 a 0 2 a 0 4 a 0 4 a 0 8 a 0 8 a 0 r e s e r v e d a 0 r e s e r v e d a 0 f u l l p a g e a 0 c a s l a t e n c y a 0 r e s e r v e d a 0 r e s e r v e d 2 a 0 3 r e s e r v e d a 0 a 6 a 5 a 4 a 0 0 0 0 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 0 0 1 t r s c t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h c l k c s r a s c a s w e r e g i s t e r s e t d a t a n e x t c o m m a n d m o d e r e g i s t e r s e t r e s e r v e d 0 0 0 0 0 a 0 a 1 2 r e s e r v e d p i n s s h o u l d b e s e t t o 0 d u r i n g m r s c y c l e . a d d r e s s b a 0 , b a 1 r e s e r v e d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 41 - revision a 01 - 002 9 .8 extended mode register set (emrs) cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 p a s r a 8 a 0 a 7 a 0 a 9 a 1 0 b a 0 a 0 a 1 1 a 0 b a 1 a 0 a 0 a 2 a 1 a 0 a 0 0 0 0 a 0 0 0 1 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 1 0 1 a 0 1 1 0 a 0 1 1 1 a 0 p a r t i a l s e l f r e f r e s h a 0 a l l b a n k s a 0 b a n k 0 , 1 ( b a 1 = 0 ) a 0 b a n k 0 ( b a 0 = b a 1 = 0 ) a 0 r e s e r v e d t r s c t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h c l k c s r a s c a s w e a d d r e s s b a 0 , b a 1 r e g i s t e r s e t d a t a n e x t c o m m a n d e x t e n d e d m o d e r e g i s t e r s e t r e s e r v e d 0 0 0 1 0 a 0 a 1 2 o u t p u t d r i v e r 0 0 0 a 0 a 6 a 5 a 0 o u t p u t d r i v e r s t r e n g t h a 0 0 0 a 0 f u l l s t r e n g t h a 0 0 1 a 0 1 / 2 s t r e n g t h a 0 1 0 a 0 1 1 a 0 1 / 4 s t r e n g t h a 0 1 / 8 s t r e n g t h 0 0 " r e s e r v e d " p i n s s h o u l d b e s e t t o " 0 " d u r i n g e m r s c y c l e r e s e r v e d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 42 - revision a 01 - 002 10 . operating timing exa mple 10 .1 interleaved bank read (burst length = 4, latency = 3) cas 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s b a 0 t r c t r c t r c t r c t r a s t r p t r a s t r p t r p t r a s t r a s t r c d t r c d t r c d t r c d t a c t a c t a c t a c t r r d t r r d t r r d t r r d a c t i v e r e a d a c t i v e r e a d a c t i v e a c t i v e a c t i v e r e a d r e a d p r e c h a r g e p r e c h a r g e p r e c h a r g e r a a r b b r a c r b d r a e r a a c a w r b b c b x r a c c a y r b d c b z r a e a w 0 a w 1 a w 2 a w 3 b x 0 b x 1 b x 2 b x 3 c y 0 c y 1 c y 2 c y 3 b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 43 - revision a 01 - 002 10 .2 interleaved bank read (burst length = 4, latency = 3, auto precharge) cas 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s b a 0 t r c t r c t r c t r a s t r p t r a s t r p t r a s t r p t r a s t r c d t r c d t r c d t r c d t a c t a c t a c t a c t r r d t r r d t r r d t r r d a c t i v e r e a d a c t i v e r e a d a c t i v e a c t i v e a c t i v e r e a d r e a d t r c r a a r b b r a c r b d r a e d q a w 0 a w 1 a w 2 a w 3 b x 0 b x 1 b x 2 b x 3 c y 0 c y 1 c y 2 c y 3 d z 0 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 a p * a p * a p * r a a c a w r b b c b x r a c c a y r b d r a e c b z
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 44 - revision a 01 - 002 10 .3 interleaved bank read (burst length = 8, latency = 3) cas 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r c t r c t r a s t r p t r a s t r p t r a s t r p t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a c r a c c a z a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a x 6 b y 0 b y 1 b y 4 b y 5 b y 6 b y 7 c z 0 c l k d q c k e d q m a d d r e s s a 1 0 b a 0 w e c a s r a s c s b a 1 a c t i v e r e a d p r e c h a r g e a c t i v e r e a d p r e c h a r g e a c t i v e t a c t a c r e a d p r e c h a r g e t a c b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 45 - revision a 01 - 002 10 .4 interleaved bank read (burst length = 8, latency = 3, auto precharge) cas a d d r e s s b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r c d t r c d t r c d t r r d t r r d a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 4 b y 5 b y 6 c z 0 r a a r a a c a x r b b r b b c b y r a c r a c c a z * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g a c t i v e r e a d a c t i v e a c t i v e r e a d t a c t a c t a c c l k d q c k e d q m a 1 0 w e c a s r a s c s r e a d a p * a p * b a 1 b a 0 t r a s t r p t r c
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 46 - revision a 01 - 002 10 .5 interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r p t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a c r a c c a z a x 0 a x 1 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 2 b y 3 b y 4 b y 5 b y 6 b y 7 c z 0 c z 1 c z 2 w r i t e p r e c h a r g e a c t i v e a c t i v e w r i t e p r e c h a r g e a c t i v e w r i t e c l k d q c k e d q m a d d r e s s a 1 0 b a 0 w e c a s r a s c s b a 1 i d l e b a n k # 0 b a n k # 1 b a n k # 2 b a n k # 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 47 - revision a 01 - 002 10 .6 interleaved bank write (burst length = 8, auto precharge) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r p t r r d t r r d r a a r a a c a x r b b r b b c b y r a c r a c c a z a x 0 a x 1 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 2 b y 3 b y 4 b y 5 b y 6 b y 7 c z 0 c z 1 c z 2 w r i t e | a p * a c t i v e a c t i v e a c t i v e w r i t e c l k d q c k e d q m a d d r e s s a 1 0 b a 0 w e c a s r a s c s b a 1 i d l e b a n k # 0 b a n k # 1 b a n k # 2 b a n k # 3 t r a s * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g t r c d t r c d t r c d a p * | w r i t e
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 48 - revision a 01 - 002 10 .7 page mode read (burst length = 4, latency = 3) cas 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t c c d t c c d t c c d t r a s t r p t r a s t r p t r c d t r c d t r r d r a a r a a c a i r b b r b b c b x c a y c a m c b z a l 0 a l 1 a l 2 a l 3 b x 0 b x 1 a y 0 a y 1 a y 2 a m 0 a m 1 a m 2 b z 0 b z 1 b z 2 b z 3 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g c l k d q c k e d q m a d d r e s s a 1 0 b a 0 w e c a s r a s c s b a 1 a c t i v e r e a d a c t i v e r e a d r e a d r e a d r e a d p r e c h a r g e t a c t a c t a c t a c t a c b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 a p *
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 49 - revision a 01 - 002 10 . 8 page mode read / write (burst length = 8, latency = 3) cas 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r a s t r p t r c d t w r r a a r a a c a x c a y a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a y 1 a y 0 a y 2 a y 4 a y 3 q q q q q q d d d d d c l k d q c k e d q m a d d r e s s a 1 0 b a 0 w e c a s r a s c s b a 1 a c t i v e r e a d w r i t e p r e c h a r g e t a c b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 50 - revision a 01 - 002 10 . 9 auto precharge read (burst length = 4, latency = 3) cas 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s b a 0 t r c t r c t r a s t r p t r a s t r p t r c d t r c d t a c a c t i v e r e a d a p * a c t i v e r e a d r a a r a b r a a c a w r a b c a x a w 0 a w 1 a w 2 a w 3 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 t a c a p * b x 0 b x 1 b x 2 b x 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 51 - revision a 01 - 002 10 .1 0 auto precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a d d r e s s a 1 0 b a 1 w e c a s r a s c s b a 0 t r c t r c t r a s t r p t r a s t r p r a a t r c d t r c d r a b r a c r a a c a w r a b c a x r a c a w 0 a w 1 a w 2 a w 3 b x 0 b x 1 b x 2 b x 3 a c t i v e a c t i v e w r i t e a p * a c t i v e w r i t e a p * * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 52 - revision a 01 - 002 10 .1 1 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 a l l b a n k s p r e c h a g e a u t o r e f r e s h a u t o r e f r e s h ( a r b i t r a r y c y c l e ) t r f c t r p t r f c c l k d q c k e d q m a d d r e s s a 1 0 w e c a s r a s c s b a 0 , b a 1
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 53 - revision a 01 - 002 10 .1 2 s elf refresh cycle 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k c s r a s c a s w e b a 0 , b a 1 a 1 0 a d d r e s s d q m c k e d q t r p t c k s t s b t c k s a r b i t r a r y c y c l e t r f c d e v i c e d e s e l e c t ( d s l ) c y c l e s e l f r e f r e s h e x i t s e l f r e f r e s h e n t r y a l l b a n k p r e c h a r g e t c k s n o t e : t h e d e v i c e e x i t t h e s e l f r e f r e s h m o d e a s y n c h r o n o u s l y a t t h e r i s i n g e d g e o f t h e c k e s i g n a l . a f t e r c k e g o e s h i g h , t h e d e v i c e d e s e l e c t o r n o - o p e r a t i o n c o m m a n d m u s t b e r e g i s t e r e d a t t h e i m m e d i a t e l y f o l l o w i n g c l k r i s i n g e d g e , a n d c k e m u s t r e m a i n h i g h a t l e a s t f o r t c k s d e l a y i m m e d i a t e l y a f t e r e x i t t h e s e l f r e f r e s h m o d e . a b u s t o f 8 k a u t o r e f e e s h c y c l e w i t h i n 7 . 8 u s b e f o r e e n t e r i n g a n d e x i t i n g i s n e c e s s a r y i f t h e s y s t e m d o e s n o t u s e t h e a u t o r e f r e s h f u n c t i o n .
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 54 - revision a 01 - 002 10 .1 3 power down mode 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 r a a c a a r a a c a x r a a r a a a x 0 a x 1 a x 2 a x 3 t s b t c k s t c k s t c k s t s b t c k s a c t i v e p o w e r d o w n m o d e e x i t p r e c h a r g e & p o w e r d o w n m o d e e n t r y d e v i c e d e s e l e c t a c t i v e n o t e : t h e p o w e r d o w n m o d e i s e n t e r e d b y a s s e r t i n g c k e " l o w " . a l l i n p u t / o u t p u t b u f f e r s ( e x c e p t c k e b u f f e r s ) a r e t u r n e d o f f i n t h e p o w e r d o w n m o d e . w h e n c k e g o e s h i g h , c o m m a n d i n p u t m u s t b e n o o p e r a t i o n a t n e x t c l k r i s i n g e d g e . v i o l a t i n g r e f r e s h r e q u i r e m e n t s d u r i n g p o w e r - d o w n m a y r e s u l t i n a l o s s o f d a t a . c l k d q c k e d q m a d d r e s s a 1 0 b a w e c a s r a s c s d s l p o w e r d o w n m o d e e x i t p o w e r d o w n m o d e e n t r y
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 55 - revision a 01 - 002 10 .1 4 burst read and single write (burst length = 4, latency = 3) cas 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k c s r a s c a s w e b a 0 b a 1 a 1 0 a d d r e s s d q m c k e d q t r c d r b a r b a c b v c b w c b x c b y c b z a v 0 a v 1 a v 2 a v 3 a w 0 a x 0 a y 0 a z 0 a z 1 a z 2 a z 3 q q q q d d d q q q q t a c t a c r e a d r e a d s i n g l e w r i t e a c t i v e b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 56 - revision a 01 - 002 10 .1 5 deep power down mode entry 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t s b t c k s a c t i v e b a n k s p r e c h a r g e c l k d q c k e d q m a d d r e s s a 1 0 b a 0 , b a 1 w e c a s r a s c s d e e p p o w e r d o w n e n t r y t r p
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 57 - revision a 01 - 002 10 .1 6 deep power down mode exit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t c k s a l l b a n k s p r e c h a r g e c l k d q c k e d q m a 1 0 a d d r e s s w e c a s r a s c s d e e p p o w e r d o w n e x i t t r p t r s c t r s c o p - c o d e o p - c o d e d s l 2 0 0 s m o d e r e g i s t e r s e t e x t e n d e d m o d e r e g i s t e r s e t a u t o r e f r e s h a u t o r e f r e s h a u t o r e f r e s h i s s u e a u t o r e f r e s h c y c l e t w o o r m o r e a r b i t r a r y c y c l e n o t e : t h e d e v i c e e x i t s t h e d e e p p o w e r d o w n m o d e a s y n c h r o n o u s l y a t t h e r i s i n g e d g e o f t h e c k e s i g n a l . a f t e r c k e g o e s h i g h , t h e d e v i c e d e s e l e c t o r n o - o p e r a t i o n c o m m a n d m u s t b e r e g i s t e r a t t h e i m m e d i a t e l y f o l l o w i n g c l k r i s i n g e d g e , a n d c k e m u s t r e m a i n h i g h a t l e a s t f o r t c k s d e l a y i m m e d i a t e l y a f t e r e x i t i n g t h e d e e p p o w e r d o w n m o d e . t r c f
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 58 - revision a 01 - 002 10 .1 7 auto precharge timing (read cycle) r e a d a p 0 1 1 1 0 9 8 7 6 5 4 3 2 1 q 0 q 0 r e a d a p a c t q 1 r e a d a p a c t q 1 q 2 a p a c t r e a d a c t q 0 q 3 ( 1 ) c a s l a t e n c y = 2 r e a d a c t a p w h e n t h e a u t o p r e c h a r g e c o m m a n d i s a s s e r t e d , t h e p e r i o d f r o m b a n k a c t i v a t e c o m m a n d t o t h e s t a r t o f i n t e r n a l p r e c g a r g i n g m u s t b e a t l e a s t t r a s ( m i n ) . d n = w r i t e d a t a , a n d q n = r e a d d a t a r e p r e s e n t s t h e r e a d w i t h a u t o p r e c h a r g e c o m m a n d . r e p r e s e n t s t h e s t a r t o f i n t e r n a l p r e c h a r g i n g . r e p r e s e n t s t h e b a n k a c t i v a t e c o m m a n d . n o t e : t r p t r p t r p ( a ) b u r s t l e n g t h = 1 c o m m a n d ( b ) b u r s t l e n g t h = 2 c o m m a n d ( c ) b u r s t l e n g t h = 4 c o m m a n d ( d ) b u r s t l e n g t h = 8 c o m m a n d d q d q d q d q q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 t r p q 0 r e a d a p a c t q 0 r e a d a p a c t q 1 q 0 r e a d a p a c t q 1 q 2 q 3 r e a d a p a c t q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 ( 2 ) c a s l a t e n c y = 3 t r p t r p t r p t r p ( a ) b u r s t l e n g t h = 1 c o m m a n d ( b ) b u r s t l e n g t h = 2 c o m m a n d ( c ) b u r s t l e n g t h = 4 c o m m a n d ( d ) b u r s t l e n g t h = 8 c o m m a n d d q d q d q d q
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 59 - revision a 01 - 002 10 .1 8 auto precharge timing (write cycle) 0 1 3 2 ( 1 ) b u r s t l e n g t h = 1 d q 4 5 7 6 8 9 1 1 1 0 w r i t e d 0 a c t a p c o m m a n d ( 2 ) b u r s t l e n g t h = 2 d q w r i t e d 0 a c t a p c o m m a n d t r p t r p d 1 ( 3 ) b u r s t l e n g t h = 4 d q w r i t e d 0 a c t a p c o m m a n d t r p d 1 ( 4 ) b u r s t l e n g t h = 8 d q w r i t e d 0 a c t a p c o m m a n d t r p d 1 d 2 d 3 d 2 d 3 d 4 d 5 d 6 d 7 t w r t w r t w r t w r 1 2 w i r t e a c t a p w h e n t h e a u t o p r e c h a r g e c o m m a n d i s a s s e r t e d , t h e p e r i o d f r o m b a n k a c t i v a t e c o m m a n d t o t h e s t a r t o f i n t e r n a l p r e c g a r g i n g m u s t b e a t l e a s t t r a s ( m i n ) . d n = w r i t e d a t a , a n d q n = r e a d d a t a r e p r e s e n t s t h e w r i t e w i t h a u t o p r e c h a r g e c o m m a n d . r e p r e s e n t s t h e s t a r t o f i n t e r n a l p r e c h a r g i n g . r e p r e s e n t s t h e b a n k a c t i v a t e c o m m a n d . n o t e :
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 60 - revision a 01 - 002 10 . 19 timing chart of read to write cycle 10 .2 0 timing chart for write to read cycle n o t e : t h e o u t p u t d a t a m u s t b e m a s k e d b y d q m t o a v o i d i / o c o n f l i c t . d n = w r i t e d a t a , a n d q n = r e a d d a t a r e a d w r i t e 1 1 1 0 9 8 7 6 5 4 3 2 1 r e a d r e a d r e a d w r i t e w r i t e d 0 d 1 d 2 d 3 w r i t e d q d q ( a ) c o m m a n d 0 d q d q d q m ( b ) c o m m a n d d q m ( b ) c o m m a n d d q m d q m d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ( 1 ) c a s l a t e n c y = 2 d q m l a t e n c y = 2 ( a ) c o m m a n d ( 2 ) c a s l a t e n c y = 3 d q m l a t e n c y = 2 i n t h e c a s e o f b u r s t l e n g t h = 4 r e a d w r i t e 0 1 1 1 0 9 8 7 6 5 4 3 2 1 q 0 r e a d q 1 q 2 q 3 r e a d r e a d w r i t e w r i t e q 0 q 1 q 2 q 3 w r i t e q 0 q 1 q 2 q 3 d 0 d 1 d q d q ( a ) c o m m a n d d q d q d q m ( b ) c o m m a n d d q m ( a ) c o m m a n d ( b ) c o m m a n d d q m d q m i n t h e c a s e o f b u r s t l e n g t h = 4 ( 1 ) c a s l a t e n c y = 2 ( 2 ) c a s l a t e n c y = 3 d 0 d 0 d 1 q 0 q 1 q 2 q 3 d 0 n o t e : d n = w r i t e d a t a , a n d q n = r e a d d a t a t l d r t l d r t l d r t l d r
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 61 - revision a 01 - 002 10 .2 1 timing chart for burst stop cycle (burst stop command) 10 .2 2 timing chart for burst stop cycle (precharge command) r e a d b s t 0 1 1 1 0 9 8 7 6 5 4 3 2 1 d q q 0 q 1 q 2 q 3 b s t ( a ) c a s l a t e n c y = 2 c o m m a n d ( b ) c a s l a t e n c y = 3 ( 1 ) r e a d c y c l e q 4 ( 2 ) w r i t e c y c l e c o m m a n d r e a d c o m m a n d q 0 q 1 q 2 q 3 q 4 q 0 q 1 q 2 q 3 q 4 d q d q w r i t e b s t n o t e : r e p r e s e n t s t h e b u r s t s t o p c o m m a n d d n = w r i t e d a t a , a n d q n = r e a d d a t a b s t 0 1 1 1 1 0 9 8 7 6 5 4 3 2 ( 1 ) r e a d c y c l e ( a ) c a s l a t e n c y = 2 c o m m a n d q 0 q 1 q 2 q 3 q 4 p r c g r e a d ( b ) c a s l a t e n c y = 3 c o m m a n d q 0 q 1 q 2 q 3 q 4 p r c g r e a d d q d q ( 2 ) w r i t e c y c l e ( a ) c a s l a t e n c y = 2 c o m m a n d q 0 q 1 q 2 q 3 q 4 p r c g w r i t e ( b ) c a s l a t e n c y = 3 c o m m a n d q 0 q 1 q 2 q 3 q 4 w r i t e d q d q d q m d q m p r c g t w r t w r n o t e : r e p r e s e n t s t h e p r e c h a r g e c o m m a n d . d n = w r i t e d a t a , a n d q n = r e a d d a t a . p r c g i n t h e c a s e o f u r s t l e n g t h = 8 w r i t e d q m l a t e n c y = 0 w r i t e d q m l a t e n c y = 0
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 62 - revision a 01 - 002 10 .2 3 cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 c k e m a s k ( 1 ) d 1 d 6 d 5 d 3 d 2 c l k c y c l e n o . e x t e r n a l i n t e r n a l c k e d q m d q 7 6 5 4 3 2 1 ( 2 ) d 1 d 6 d 5 d 3 d 2 c l k c y c l e n o . e x t e r n a l i n t e r n a l c k e d q m d q 7 6 5 4 3 2 1 ( 3 ) d 1 d 6 d 5 d 4 d 3 d 2 c l k c y c l e n o . e x t e r n a l c k e d q m d q d q m m a s k d q m m a s k c k e m a s k c k e m a s k i n t e r n a l c l k c l k c l k n o t e ) d n = w r i t e d a t a , a n d q n = r e a d d a t a
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 63 - revision a 01 - 002 10 .2 4 cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q 1 q 6 q 4 q 3 q 2 c l k c y c l e n o . e x t e r n a l i n t e r n a l c k e d q m d q o p e n o p e n 7 6 5 4 3 2 1 q 1 q 6 q 3 q 2 c l k c y c l e n o . e x t e r n a l i n t e r n a l c k e d q m d q o p e n ( 2 ) 7 6 5 4 3 2 1 q 1 q 6 q 2 c l k c y c l e n o . e x t e r n a l i n t e r n a l c k e d q m d q q 5 q 4 ( 3 ) q 4 c l k c l k c l k q 3 n o t e ) d n = w r i t e d a t a , a n d q n = r e a d d a t a
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 64 - revision a 01 - 002 1 1 . package dimension 1 1 .1 : lpsdr x 16 vbga54 b all ( 8x9 mm^2, ball pitch:0.8mm) n o t e : 1 . b a l l l a n d : 0 . 5 m m . b a l l o p e n i n g : 0 . 4 m m . p c b b a l l l a n d s u g g e s t e d Q 0 . 4 m m 2 . d i m e n s i o n s a p p l y t o s o l d e r b a l l s p o s t - r e f l o w . t h e p r e - r e f l o w d i a m e t e r i s 0 . 4 2 o n a 0 . 4 s m d b a l l p a d
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 65 - revision a 01 - 002 1 1 . 2 : lpsdr x 32 vbga90 b all ( 8x13 mm^2, ball pitch:0.8mm) n o t e : 1 . b a l l l a n d : 0 . 5 m m . b a l l o p e n i n g : 0 . 4 m m . p c b b a l l l a n d s u g g e s t e d Q 0 . 4 m m 2 . d i m e n s i o n s a p p l y t o s o l d e r b a l l s p o s t - r e f l o w . t h e p r e - r e f l o w d i a m e t e r i s 0 . 4 2 o n a 0 . 4 s m d b a l l p a d .
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 66 - revision a 01 - 002 1 2 . o rdering information w 9 8 8 d 6 f b g x 6 i mobile lpddr/lpsdr sdram package part numbering product line 98:mobile lpsdr sdram 94:mobile lpddr sdram density 7:2 7 =128m 8:2 8 =256m 9:2 9 =512m power supply d:1.8/1.8 v dd / v ddq i/o ports width 6:16bit 2:32bit temperature with standard idd6 g: - 25c~85c package material x: lead - free + halogen - free package or kgd k: kgd b: bga package configuration code g: 54vfbga, 8mmx9mm h: 60vfbga, 8mmx9mm j: 90vfbga, 8mmx13mm generation design revision. with low power idd6 e: - 25c~85c i: - 40c~85c clock rate 5:5ns ? ? ? part number v dd /v ddq i/o width package others w988d6fbgx6i 1.8v/1.8v 16 54vfbga 166mhz, -40c~85c, low power w988d6fbgx6e 1.8v/1.8v 16 54vfbga 166mhz, -25c~85c, low power w988d6fbgx7e 1.8v/1.8v 16 54vfbga 133mhz, -25c~85c, low power w988d6fbgx7g 1.8v/1.8v 16 54vfbga 133mhz, -25c~85c w988d2fbjx6i 1.8v/1.8v 32 90vfbga 166mhz, -40c~85c, low power W988D2FBJX6E 1.8v/1.8v 32 90vfbga 166mhz, -25c~85c, low power w988d2fbjx7e 1.8v/1.8v 32 90vfbga 133mhz, -25c~85c, low power w988d2fbjx7g 1.8v/1.8v 32 90vfbga 133mhz, -25c~85c
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 67 - revision a 01 - 002 1 3. revision history version date page description a 01 - 001 0 4 / 28 /20 11 all product datasheet for customer . a01 - 002 05 / 18/2011 9 ~11 update idd4r & idd4w value & add normal power grade.
w98 8 d 6 fb / w98 8 d 2 fb 2 56 m b m obile lps dr publication release date : may, 18 , 2011 - 68 - revision a 01 - 002 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wher e in personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. ----------------------------------------------------------------------------------------------------------------------------- -------------------- please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in the datasheet belong to their respective owners.

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